1 Module Overview

The Sigma-Delta Analog-to-Digital Converter (SDADC) converts an analog voltage to a signed 16-bit value by integrating and decimating the output of a Sigma-Delta modulator. The filtering and decimation are done using a sinc-based filter that has zeros placed to minimize the aliasing effects of the decimation. This is a 3rd order sinc filter with an adjustable Over Sampling Ratio (OSR) to achieve higher throughput, as shown in the figure below. For example, an OSR of 64 will provide an output at 23 ksps while an OSR of 1024 will produce an output at a sample rate of 1.4 ksps.

The SDADC provides a signed result in a 24-bit register to allow for gain and offset correction without overflow in hardware. Because the result is in 2’s complement format, the SDADC result is signed 16-bit (maximum) using ±VREF. Using the internal VREF set at 1.024V, the SDADC will produce codes for ±1.024V. The internal VREF can be configured to supply a reference of 1.024V, 2.048V, and 4.096V.