2 Functional Description
The Sigma-Delta Analog-to-Digital Converter (SDADC) can be used for high-resolution ADC measurements, and these measurements can include: Temperature sensors, Thermocouples, Cold-Junction Compensation, 3-4 Wire RTD sensors, 4-20 mA current loops, current (Shunt), as well as scales and load cells. The Sigma-Delta architecture provides a low-cost solution for these precision measurements that requires only a simple R-C low-pass filter for anti-aliasing.
A generic clock (GCLK_SDADC) is used to generate the CLK_SDADC through a 7-bit prescaler. The GCLK must be configured and enabled before using the SDADC. The sampling clock is derived from the CLK_SDADC/4. Therefore, the maximum CLK_SDADC is 6 MHz, as the maximum sampling frequency is 1.5 MHz. The GCLK_SDADC is asynchronous to the APB bus clock, therefore, writes to registers require synchronization. This generic clock allows configuring CLK_SDADC to run in sleep modes based on the values of RUNSTDBY (Run in Standby), ONDEMAND (On Demand Control) and ENABLE (Enable) bits of the CTRLA (Control A) register. The 7-bit prescaler enables flexible sampling frequency adjustment.
The SDADC supports differential measurements on three analog input channels which can be used sequentially. The measurements are done using any one of four references: internal bandgap, external voltage on VREFB (Voltage Reference) pin, Digital-to-Analog Converter (DAC) output, or VDD Analog (VDDANA). The voltage reference has a selectable buffer to offer higher input impedance to the external reference.
The SDADC filters and decimates the Sigma-Delta output bit stream at 16-bit (signed) with programmable rates of CLK_SDADC_FS (prescaled SDADC clock frequency) divided by 64 to 1024. The Output rate is set by modifying the programmable Over Sampling Ratio (OSR). The result is a 2’s compliment 24-bit result with programmable gain and offset correction.
- Result Ready Interrupt (RESRDY) – The RESRDY can trigger a DMA transfer or event.
- Overrun Interrupt (OVERRUN) – The OVERRUN flag is set when the previous result is not read before a new result is ready.
- Window Monitor Interrupt (WINMON) – The WINMON can generate an event by setting the WINMONEO bit in the EVCTRL register.
Automatic sequences can be configured to enable multiple samples from a single start of conversion request. The order of this conversion is from the lower positive input pair to the upper positive input pair (AINN0, AINP0, AINN1, AINP1 ...).