2.10 Serial Clock (SCL) Source and Configuration

The Serial Clock (SCL) signal is generated by module hardware via the I²C Clock Selection (I2CxCLK) Register, the I2C Baud Rate Prescaler (I2CxBAUD) Register, and the Fast Mode Enable (FME) bits. This differs from the MSSP configuration which uses the Synchronous Serial Port Mode Select (SSPM) bits and the MSSP Baud Rate Divider and Address (SSPxADD) register to generate the SCL signal.

The figure below illustrates the SCL clock generation.

Figure 2-1. SCL Clock Generation

I2CxCLK contains several clock source selections. The clock source selections typically include variants of the system clock and timer resources.

Important: When using a timer as the clock source, the timer must also be appropriately configured. Additionally, when using the HFINTOSC as a clock source, it is important to understand that the HFINTOSC frequency selected by the OSCFRQ register is used as the clock source. The clock divider selected by the New Divider Selection Request (NDIV) bits is not used. For example, if OSCFRQ selects 4 MHz as the HFINTOSC clock frequency, and the NDIV bits select a divide by four scaling factor, the I2C Clock Frequency will be 4 MHz and not 1 MHz since the divider is ignored.

I2CxBAUD is used to determine the prescaler (clock divider) for the I2CxCLK source.

The FME bits act as a secondary divider to the prescaled clock source.

The equation below shows the method to calculate the SCL frequency.

Equation 2-1. SCL Frequency Calculation

f_{S C L} = \frac{\frac{f_{I 2 C C L K}}{(B A U D + 1)}}{F M E} w h e r e : f_{S C L} = S e r i a l C l o c k (S C L) f r e q u e n c y f_{I 2 C C L K} = F r e q u e n c y o f t h e c l o c k s o u r c e s e l e c t e d b y I 2 C C L K B A U D = \Pr e s c a l e r (c l o c k d i v i d e r) f o r t h e I 2 C C L K s o u r c e F M E = S e c o n d a r y d i v i d e r t o t h e p r e s c a l e d I 2 C C L K s o u r c e

When FME = 00, one SCL period (T_SCL) is equal to five clock periods of the prescaled I2CxCLK source. In other words, the prescaled I2CxCLK source is divided by five. For example, if the HFINTOSC (set to 4 MHz) clock source is selected, I2CxBAUD is loaded with a value of ‘7’ and the FME bits are clear, the actual SCL frequency is 100 kHz (SCL Frequency (FME = 00)).

SCL Frequency (FME = `00`)

I2CxCLK: HFINTOSC (4 MHz)
I2CxBAUD: 7
FME: 00

f_{S C L} = \frac{\frac{f_{I 2 C C L K}}{(B A U D + 1)}}{F M E} = \frac{\frac{4 M H z}{8}}{5} = 100 k H z

When FME = 00, host hardware uses the first prescaled I2CxCLK source period to release SCL, allowing it to float high (Figure 2-2). Host hardware then uses the second and third periods to sample SCL to verify that SCL is high. If a client is holding SCL low (clock stretch) during the second and/or third period, host hardware samples each successive prescaled I2CxCLK period until a high level is detected on SCL. Once the high level is detected, host hardware samples SCL during the next two I2CxCLK periods to verify that SCL is high. The host hardware then uses the fourth prescaled I2CxCLK source period to drive SCL low. During the fifth period, host hardware verifies that SCL is in fact low.

Figure 2-2. SCL Timing (FME = 00)

When FME = 01, one SCL period (T_SCL) is equal to four clock periods of the prescaled I2CxCLK source. In other words, the prescaled I2CxCLK source is divided by four. Using the example from above, if the HFINTOSC (4 MHz) clock source is selected, I2CxBAUD is loaded with a value of ‘7’, and FME = 01, the actual SCL frequency is 125 kHz (SCL Frequency (FME = 01)).

SCL Frequency (FME = `01`)

I2CxCLK: HFINTOSC (4 MHz)
I2CxBAUD: 7
FME: 01

f_{S C L} = \frac{\frac{f_{I 2 C C L K}}{(B A U D + 1)}}{F M E} = \frac{\frac{4 M H z}{8}}{4} = 125 k H z

When FME = 01, host hardware uses the first prescaled I2CxCLK source period to release SCL, allowing it to float high (Figure 2-3). Host hardware then uses the second period to sample SCL to verify that SCL is high. If a client is holding SCL low (clock stretch) during the second period, host hardware samples each successive prescaled I2CxCLK period until a high level is detected on SCL. Once the high level is detected, host hardware samples SCL during the next period to verify that SCL is high. The host hardware then uses the third period to drive SCL low. During the fourth prescaled period, host hardware verifies that SCL is in fact low.

Figure 2-3. SCL Timing (FME = 01)

When FME = 10, one SCL period (T_SCL) is equal to sixteen clock periods of the prescaled I2CxCLK source. In other words, the prescaled I2CxCLK source is divided by 16. In SCL Frequency (FME = 10), when the HFINTOSC (64 MHz) clock source is selected, I2CxBAUD is loaded with a value of ‘3’, and FME = 10, the actual SCL frequency is 1 MHz.

SCL Frequency (FME = `10`)

I2CxCLK: HFINTOSC (64 MHz)
I2CxBAUD: 3
FME: 10

f_{S C L} = \frac{\frac{f_{I 2 C C L K}}{(B A U D + 1)}}{F M E} = \frac{\frac{64 M H z}{4}}{16} = 1 M H z

When FME = 10, host hardware uses the first prescaled I2CxCLK source period to release SCL, allowing it to float high (Figure 2-4). Host hardware then uses the sixth period to sample SCL to verify that SCL is high. If a client is holding SCL low (clock stretch) during the sixth period, host hardware samples each successive prescaled I2CxCLK period until a high level is detected on SCL. Once the high level is detected, host hardware samples SCL during the next six I2CxCLK periods to verify that SCL is high. The host hardware then uses the seventh prescaled I2CxCLK source period to drive SCL low. During eighth through sixteenth periods, host hardware verifies that SCL is in fact low.

Figure 2-4. SCL Timing (FME = 10)

The following tables show the different FME Bit Options and Common I2CBAUD Divider Settings for different modes of I²C operation.