2.3 Clock Stretching Hardware

Clock stretching allows a client device to hold the clock line, preventing further bus communication. This allows time for the client device, which may be operating at a slower speed than the host, to process data. The client device can hold the clock line low until it is ready to continue communications.

Clock stretching in the stand-alone I²C module can be enabled or disabled via the Clock Stretching Disable (CSD) bit. Clock stretching can be performed under several conditions:

• Buffer read/write operations – If the RXBF bit is set (receive buffer full), or the TXBE bit is set (transmit buffer empty) and clock stretching is enabled (CSD = 0), the clock will be stretched on the 8^th falling SCL edge, allowing user software to either read the incoming data from the receive buffer or write data to the transmit buffer.
• Incoming address match interrupt – When a matching address is received and the Address Interrupt and Hold (ADRIE) Enable bit is set, the Client Clock Stretching (CSTR), Address Interrupt Flag (ADRIF), and the generic I²C Interrupt Flag (I2CxIF) bits are set, and the SCL line is stretched following the 8^th falling clock edge. This allows software to read the address from the either the I2CxADB0/1 registers (when ABD = 0) or I2CxRXB register (when ABD = 1), and choose whether to ACK or NACK the incoming address. When the operation is complete, software clears the CSTR and ADRIF bits. The incoming address match interrupt is similar to the MSSP’s Address Hold Enable (AHEN) bit functionality.
• Data write interrupt – The Data Write Interrupt and Hold (WRIE) Enable bit enables clock stretching upon the reception of a data byte. When the WRIE bit is set and a data byte is received, the CSTR, Data Write Interrupt Flag (WRIF), and I²C Interrupt Flag (I2CxIF) bits are set, and the SCL line is stretched following the 8^th falling clock edge. This allows for software to determine whether to ACK or NACK the incoming data byte. Clock stretching is released when software clears the CSTR bit. Software must also clear the WRIF bit to resume normal operation. The data write interrupt is similar to the MSSP’s Data Hold Enable (DHEN) bit functionality.
• Acknowledge status – The Acknowledge Status Time Interrupt and Hold (ACKTIE) Enable bit is used to enable clock stretching after the ACK phase of transmission. The ACKTIE bit enables clock stretching for all address/data transactions – address, write or read. Following the ACK sequence (9^th falling edge of SCL), the CSTR, Acknowledge Status Time Interrupt Flag (ACKTIF), and I²C Interrupt Flag (I2CxIF) bits are set, and the SCL line is stretched. Once the client has completed its processing of the ACK sequence, software must clear CSTR to release the SCL line. Software must also clear the ACKTIF bit to resume normal operation. The Acknowledge status feature is similar to the MSSP’s Stretch Enable (SEN) bit, which would stretch the clock upon the 9^th falling edge of SCL.