2 Differences Between the MSSP and Stand-Alone I2C Modules

The stand-alone I2C module has several important differences when compared to Microchip's Host Synchronous Serial Port (MSSP) module:

  • Dedicated Address, Receive, and Transmit Buffers
  • Interrupts for Address Match, Transmit Buffer Empty, Receive Buffer Full, Bus Time-out, Data Byte Count, Acknowledge and Not Acknowledge
  • Clock Stretching Hardware for:
    • RX buffer full
    • TX buffer empty
    • Address match
    • Acknowledgment
  • Hardware Supported Bus Time-out Detection
  • Data Byte Counter
  • Programmable SDA Hold Time
  • Programmable Bus Free Time
  • Dedicated I2C Pad Control Registers
  • TRIS Register Setting
  • Serial Clock (SCL) Source and Configuration
Table 2-1. Comparison Between Stand-Alone I2C and MSSP Modules
FeatureI2CMSSP
Buffers/Registers
Address BuffersI2CxADB0I2CxADB1SSPxADD
I2CxADR0I2CxADR1
I2CxADR2I2CxADR3
Transmit BufferI2CxTXBSSPxBUF
Receive BufferI2CxRXBSSPxBUF
Byte CountI2CxCNT, I2CxCON3None
Bus Time-OutI2CxBTO, I2CxBTOCNone
I2C Module ControlI2CxCON0SSPxCON1
I2CxCON1SSPxCON2
I2CxCON2SSPxCON3
I2CxCON3None
I2C Interrupt ControlI2CxPIEPIExPIEx
I2CxPIRPIRxPIRx
I2C Error ControlI2CxERRPIEx
PIRx
SSPxCON1
I2C StatusI2CxSTAT0I2CxSTAT1SSPxSTAT
I2CxCON1SSPxCON2
I2C Pad ControlRxyI2CRxyI2C(1)
Interrupt bits
Byte Count CNTIF, I2CxIFNone
ACK DetectACKTIF, I2CxIFSSPxIF
Data WriteWRIF, RXIF, I2CxIFSSPxIF
Address MatchADRIF, I2CxIFNone
Start ConditionSCIF, I2CxIFSCIF, SSPxIF
Restart ConditionRSCIF, I2CxIFSCIF, SSPxIF
Stop ConditionPCIF, I2CxIFPCIF, SSPxIF
Transmit Buffer EmptyTXIF, I2CxIFSSPxIF
Receive Buffer FullRXIF, I2CxIFSSPxIF
Bus Time-OutBTOIF, I2CxEIFNone
Bus CollisionBCLIF, I2CxEIFBCLxIF, SSPxIF
NACK DetectNACKIF, I2CxEIFSSPxIF
Status Bits
Bus Free IndicationBFRENone
Host Mode ActiveMMANone
Client Mode ActiveSMANone
Host Data RequestMDRNone
Acknowledge StatusACKSTATACKSTAT
Acknowledge Time StatusACKTACKTIM
Receive OverflowRXOSSPOV
Transmit UnderflowTXUNone
Transmit Write ErrorTXWEWCOL
Transmit Buffer EmptyTXBEBF
Receive Read ErrorRXRENone
Receive Buffer FullRXBFBF
Data/Address Indicator DD/A
Read/Write IndicatorRR/W
Enable/Action Bits
Module EnableENSSPxEN
Restart EnableRSENRSEN
Initiate Start ConditionWhen: SEN
ABD = 0: Write to I2CxTXB - Hardware sets S
ABD = 1: Software sets S
Initiate Restart ConditionWhen: RSEN
ABD = 0: Write to I2CxTXB - Hardware sets S (when RSEN = 1)
ABD = 1: Software sets S (when RSEN = 1)
Initiate Stop ConditionP, HardwarePEN
Enable Clock StretchingCSDSEN
Clock Stretch ReleaseCSTRCKP
General Call EnableGCENGCEN
Enable Acknowledge SequenceHardwareACKEN
Receive EnableENRCEN
Clock Source and ConfigurationI2CxCLK, FME, I2CxBAUDSSPM, SSPxADD
SDA Hold TimeSDAHTSDAHT
Bus Free Time ConfigurationBFRETNone
Bus Time-Out ConfigurationI2CxBTO, I2CxBTOCNone
Byte Count ConfigurationI2CxCNT, ACNT, ACNTMDNone
Address Hold EnableADRIEAHEN
Data Hold EnableWRIEDHEN
SCL/SDA Pin Control
Weak Pull-up ControlPU<1:0> bits of RxyI2CWPUx Register
Use of internal pull-ups on bus?YesYes(1)
Input Threshold ControlTH<1:0> bits of RxyI2CINLVLx Register
SMBus Threshold ControlTH<1:0> bits of RxyI2CCKE bit of SSPxSTAT Register
Slew Rate ControlSLEW bit of RxyI2CSMP bit of SSPxSTAT Register
Pin Direction ControlTRIS (TRIS = 0)TRIS (TRIS = 1)
Open-Drain ControlODCONx RegisterHardware Control
Note:
  1. The RxyI2C register is only available on select devices that contain the MSSP module(s). For devices that do not utilize the RxyI2C registers, internal Weak Pull-up resistors are not recommended for use, and input threshold levels and slew-rate control are determined by the INVLV and SLRCON registers, respectively.