5.1 Timing Diagram Values

The following table lists the timing diagram values of the XIFM gate driver.

Note: Condition V_SUP = 24V, Temp. = 0 °C to 85 °C.

Table 5-1. Timing Diagram Values
Parameter		Description	Min.	Typ.	Max.	Unit
Minimum pulse width		T_MIN⁸	—	—	—	ns
Propagation delay		T_PD^{1, 3}	—	—	280	ns
De-glitch time		T_DG⁴	—	200	—	ns
Rise time		T_R^{2, 3}	—	35	—	ns
Fall time		T_F^{2, 3}	—	30	—	ns
Two-level turn-on	First step turn-on time	T_ON1⁴	—	200	—	ns
Two-level turn-on	First step turn-on voltage	V_TON1⁴	—	9.5	—	V
Multi-level turn-off step	First step turn-off time	T_OFF1⁴	—	200	—	ns
	First step turn-off voltage	V_OFF1,⁴	—	9.5	—	V
	Second step turn-off time	T_OFF2⁴	—	200	—	ns
	Second step turn-off voltage	V_OFF2⁴	—	4.5	—	V
DSAT voltage level		V_DSAT⁴	—	8.7	—	V
DSAT blanking time		T_DSAT^{4, 5}	1000	1100	1200	ns
DSAT de-glitch time		T_{DSAT_DG}⁴	—	0	—	ns
DSAT turn-off steps	First step DSAT turn-off time	T_OFFD1⁴	—	250	—	ns
	First step DSAT turn-off voltage	V_OFFD1⁴	—	9.5	—	V
	Second step DSAT turn-off time	T_OFFD2⁴	—	250	—	ns
	Second step DSAT turn-off voltage	V_OFFD2⁴	—	6.5	—	V
	Third step DSAT turn-off time	T_OFFD3⁴	—	250	—	ns
	Third step DSAT turn-off voltage	V_OFFD3⁴	—	2.5	—	V
Fault time delay		T_FLT⁷	—	5000	—	ns
Fault reset		T_{FLT_RST}	—	1000	—	ns
Dead time-input		T_DEAD⁶	—	500	—	ns
Reset timing		T_RST,Minimum reset time	—	1000	—	ns
Automatic reset (optional)		—	—	5	—	ms

Note:

Measured from 50% to 50% of input trigger and output V_GS signal.
Measured from 10% to 90% of output V_GS signal.
Measured without augmented settings and at no load condition.
Software configurable depends on user requirements.
Hardware blanking time is set to the present value in the table.
Death Time must be configured by the user by the host controller.
This is fault output delay time, but when DSAT is detected on board gate driver shouts-down trigger within 25 ns.
The minimum pulse width is a factor of the multi-level turn-off and two-level turn-on time.