2.6 Shutdown Input (SHDN) and Input UVLO

The SHDN input is an active-low input signal that turns the LDO ON or OFF. The SHDN threshold has a logic HIGH level of minimum 1.13V and a logic LOW level of maximum 0.79V.

The SHDN pin ignores low-going pulses that are up to 10 µs. This blanking window helps to reject any system noise spikes on the SHDN input signal. Then, on the rising edge of the SHDN input, the shutdown circuitry adds 600 µs delay before allowing the regulator output to turn ON. This delay helps to reject any false turn-on signals or noise on the SHDN input signal. After the (10 + 600) µs delay, the regulator starts charging the load capacitor as the output rises from 0V to its regulated value. The charging current amplitude will be limited by the short circuit current value of the device. If the SHDN input signal is pulled low during the 610 µs delay period, the timer will be reset, and the delay time will start over again on the next rising edge of the SHDN input. Figure 2-2 shows a timing diagram of the SHDN input.

The MCP1781 has an internal discharge transistor connected to the VOUT Pin that is enabled when the SHDN pin goes low. The discharge occurs through a typical resistance of 105Ω.

The UVLO block helps prevent false start-ups during the power-up sequence, until the input voltage reaches a value of 2.7V. The minimum input voltage required for normal operation needs to take into account the dropout voltage for the specific output voltage and output current conditions.