11.5.3 Interrupt Control
| Name: | INTCTRL |
| Offset: | 0x04 |
| Reset: | 0x00 |
| Property: | - |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| FLREADY | EEREADY | ||||||||
| Access | R/W | R/W | |||||||
| Reset | 0 | 0 |
Bit 1 – FLREADY Flash Ready Interrupt Enable
Writing a ‘1’ to this bit enables the interrupt,
which indicates that the Flash is ready for new write/erase operations.
This is a level interrupt that will be triggered only when the
FLREADY flag in the INTFLAGS register is set to ‘1’. Thus, the
interrupt must not be enabled before triggering an NVM command, as the FLBUSY
flag will not be set before the NVM command is issued. The interrupt must be
disabled in the interrupt handler.
Bit 0 – EEREADY EEPROM Ready Interrupt Enable
Writing a ‘1’ to this bit enables the interrupt,
which indicates that the EEPROM is ready for new write/erase operations.
This is a level interrupt that will be triggered only when the EEREADY flag in
the INTFLAGS register is set to ‘1’. Thus, the interrupt must
not be enabled before triggering an NVM command, as the EEBUSY flag will not be
set before the NVM command is issued. The interrupt must be disabled in the
interrupt handler.