4.3.6 Special Considerations

JTAG interface

On some Microchip AVR UC3 devices the JTAG port is not enabled by default. When using these devices it is essential to connect the RESET line so that the Power Debugger can enable the JTAG interface.

aWire interface

The baud rate of aWire communications depends upon the frequency of the system clock, since data must be synchronized between these two domains. The Power Debugger will automatically detect that the system clock has been lowered, and re-calibrate its baud rate accordingly. The automatic calibration only works down to a system clock frequency of 8 kHz. Switching to a lower system clock during a debug session may cause contact with the target to be lost.

If required, the aWire baud rate can be restricted by setting the aWire clock parameter. Automatic detection will still work, but a ceiling value will be imposed on the results.

Any stabilizing capacitor connected to the RESET pin must be disconnected when using aWire since it will interfere with correct operation of the interface. A weak external pull-up (10 kΩ or higher) on this line is recommended.

Shutdown sleep mode

Some AVR UC3 devices have an internal regulator that can be used in 3.3V supply mode with 1.8V regulated I/O lines. This means that the internal regulator powers both the core and most of the I/O. Only Microchip AVR ONE! debugger supports debugging while using sleep modes where this regulator is shut off.