20.9.5 TC0 Counter Value Register
When addressing I/O Registers as data space using LD and ST instructions, the provided offset must be used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an I/O address offset within 0x00 - 0x3F.
| Name: | TCNT0 |
| Offset: | 0x46 |
| Reset: | 0x00 |
| Property: | When addressing as I/O Register: address offset is 0x26 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| TCNT0[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bits 7:0 – TCNT0[7:0] TC0 Counter Value
The Timer/Counter Register gives direct access, both for read and write operations, to the Timer/Counter unit 8-bit counter. Writing to the TCNT0 Register blocks (removes) the Compare Match on the following timer clock. Modifying the counter (TCNT0) while the counter is running, introduces a risk of missing a Compare Match between TCNT0 and the OCR0x Registers.