11.2 Peripheral DMA Controller (PDC)

Features of the PDC include:

• Data Transfer Handling between Peripherals and Memories
• Low Bus Arbitration Overhead
  • One Main System Bus clock cycle needed for a transfer from memory to peripheral
  • Two Main System Bus clock cycles needed for a transfer from peripheral to memory
• Next Pointer Management Reduces Interrupt Latency Requirement

The PDC handles transfer requests from the channel according to the priorities given in the following tables (low-to-high priorities).