40.4.8.3 PDC Mode

The Peripheral DMA Controller (PDC) can be used in association with the AES to perform an encryption/decryption of a buffer without any action by software during processing.

AES_MR.SMOD must be configured to 2.

For all operating modes except CBC-MAC (AES_MR.LOD=1), 2 DMA channels must be programmed (transmit and receive). In CBC-MAC, only 1 transmit channel must be programmed.

The sequence order is as follows:

1. Write AES_MR with all required fields, including but not limited to SMOD and OPMOD.
2. Write the key.
3. Write the initialization vector or counter in AES_IVRx.
   Note: IVRx concerns all modes except ECB.
4. Set the Transmit Pointer register (AES_TPR) to the address where the data buffer to encrypt/decrypt is stored and the Receive Pointer register (AES_RPR) where it must be encrypted/decrypted.
   Note: Transmit and receive buffers can be identical.
5. Set the Transmit and the Receive Counter registers (AES_TCR and AES_RCR) to the same value. This value must be a multiple of the data transfer type size (see the following table).
   Note: The same requirements are necessary for the Next Pointer(s) and Counter(s) of the PDC (AES_TNPR, AES_RNPR, AES_TNCR, AES_RNCR).
6. If not already done, set AES_IER.ENDRX (or AES_IER.RXBUFF if the next pointers and counters are used), depending on whether an interrupt is required or not at the end of processing.
7. Enable the PDC in transmission and reception to start the processing (AES_PTCR).

When the processing completes, AES_ISR.ENDRX (or AES_ISR.RXBUFF) is raised. If an interrupt has been enabled by setting the corresponding bit in AES_IER, the interrupt line of the AES is activated.

When PDC is used, the data size to transfer (byte, half-word or word) depends on the AES mode of operations. This size is automatically configured by the AES.