9 general-purpose GPNVM bits for device Booting option
Safety and Security
128 lock bits, each protecting a lock region
One non-volatile bit for code and device protection
User signature blocks of 4 Kbytes secured with locks or access
rights
Cryptographic key transfer from user signature area to AES engine over private key bus
One Time Programmable (OTP) block for software monotonic counter
Erase Function Lock (EFL) to disable the chip hardware Erase
signal
Register write and command protection
Program Verify and Erase Verify Fail self-checking mechanism
ECC single and multiple error flags report
Erase and Write Operations
Write by page
Software erase by block (4 Kbytes), multiple blocks or
sector
Full chip erase by hardware Erase signal
Suspend and resume of write and erase operations
Read Operations
High performance in Thumb-2 mode with 128-bit-wide memory
interface
Code loop and code read optimization
Automatic Clock-off mode for power reduction
Supports read of the calibration bits
The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.
