42.4.9.3 PDC Mode

The Peripheral Data Controller (PDC or Peripheral DMA Controller) can be used in association with the SHA to perform the algorithm on a complete message without any action by software during processing.

In this mode, the type of data transfer is set in words.

The sequence is as follows:

1. Set the Transmit Pointer register (SHA_TPR) to the address where the data buffer to process is stored.
2. Set the Transmit Counter registers (SHA_TCR) to the same value. This value must be a multiple of words.
   Note: The same requirements are necessary for the Next Pointer(s) and Counter(s) of the PDC (SHA_TNPR, SHA_TNCR).
3. If not already done, set SHA_IER.ENDTX (or TXBUFF if the next pointers and counters are used), depending on whether an interrupt is required at the end of processing.
4. If not already done, set SHA_IER.DATRDY.
5. Set the FIRST command by writing a ‘1’ into the corresponding bit of the SHA_CR.
   Note: The FIRST bit command is also used to resume after message processing was interrupted. When a first message processing is interrupted to process another message, the intermediate hash results must be stored in the system memory and they must be reloaded in user initial values registers (IR0 accessed via SHA_IDATAR when SHA_CR.WUIHV=1) prior to resume and continue the processing of the first message. Thus, the PDC data buffers and SHA_CR.FIRST command must be managed accordingly.
6. Enable the PDC in transmission to start the processing (SHA_PTCR).
7. When the processing completes, ENDTX (or TXBUFF) in the SHA_ISR rises. If an interrupt has been enabled by setting the corresponding bit in SHA_IER, the interrupt line of the SHA is activated.
8. As soon as ENDTX (or TXBUFF) or interrupt is triggered, the DATRDY bit or interrupt line must be triggered.
9. The message digest can be read from the Output Data registers (SHA_IODATARx read-only registers).