28.3.1 Chip ID Register
| Name: | CHIPID_CIDR |
| Offset: | 0x0 |
| Reset: | – |
| Property: | Read-only |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| EXT | NVPTYP[2:0] | ARCH[7:4] | |||||||
| Access | R | R | R | R | R | R | R | R | |
| Reset | – | – | – | – | – | – | – | – | |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| ARCH[3:0] | SRAMSIZ[3:0] | ||||||||
| Access | R | R | R | R | R | R | R | R | |
| Reset | – | – | – | – | – | – | – | – | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| NVPSIZ2[3:0] | NVPSIZ[3:0] | ||||||||
| Access | R | R | R | R | R | R | R | R | |
| Reset | – | – | – | – | – | – | – | – | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| EPROC[2:0] | VERSION[4:0] | ||||||||
| Access | R | R | R | R | R | R | R | R | |
| Reset | – | – | – | – | – | – | – | – | |
Bit 31 – EXT Extension Flag
| Value | Description |
|---|---|
| 0 | Chip ID has a single register definition without extension. |
| 1 | An extended Chip ID exists. |
Bits 30:28 – NVPTYP[2:0] Nonvolatile Program Memory Type
Bits 27:20 – ARCH[7:0] Architecture Identifier
| Value | Name | Description |
|---|---|---|
| 0xC3 | PIC32CXMTSH128 | Dual Core, Single Phase, High Accuracy (128-lead version) |
Bits 19:16 – SRAMSIZ[3:0] Internal SRAM Size
| Value | Name | Description |
|---|---|---|
| 0–11 | – | Reserved |
| 12 | 128K | 128 Kbytes |
| 13 | 256K | 256 Kbytes |
| 14 | – | Reserved |
| 15 | 512K | 512 Kbytes |
Bits 15:12 – NVPSIZ2[3:0] Second Nonvolatile Program Memory Size
Bits 11:8 – NVPSIZ[3:0] Nonvolatile Program Memory Size
| Value | Name | Description |
|---|---|---|
| 0–9 | – | Reserved |
| 10 | 512K | 512 Kbytes |
| 11 | – | Reserved |
| 12 | 1024K | 1024 Kbytes |
| 13 | – | Reserved |
| 14 | 2048K | 2048 Kbytes |
| 15 | – | Reserved |
Bits 7:5 – EPROC[2:0] Embedded Processor
Bits 4:0 – VERSION[4:0] Version of the Device
Current version of the device.