31.5 Functional Description

The memory to memory transfer requires two operations.

The PDC receive channel associated to the MEM2MEM module must be configured with the transfer destination address and buffer size.

The PDC transmit channel associated to the MEM2MEM module must be configured with the source address and buffer size. The transmit channel buffer size must be equal to the receive channel buffer size.

The two PDC channels exchange data through the Transfer Holding register (MEM2MEM_THR) which appears fully transparent from configuration. This register can be used as a general-purpose register in case the memory to memory transfer capability is not used.

The size of each element of the data buffer can be configured in byte, half-word or word by writing the TSIZE field in the Mode register (MEM2MEM_MR). Word transfer (32-bit) is the default size.

The transfer ends when either RXEND rises and/or RXBUFF rises in the Interrupt Status register (MEM2MEM_ISR).

An interrupt can be triggered at the end of transfer by configuring the Interrupt Enable register (MEM2MEM_IER). Refer to the section “Peripheral Data Controller (PDC)”.