Jump to main content
Second-Generation Smart Energy Platform Solution including Integrated Metrology, Dual Arm® Cortex®-M4F Cores, Security and LCD Controller
Second-Generation Smart Energy Platform Solution including Integrated Metrology, Dual Arm® Cortex®-M4F Cores, Security and LCD Controller
Product Pages
PIC32CX1025MTSH PIC32CX2051MTSH PIC32CX5112MTSH
  1. Home
  2. 34 Flexible Serial Communication Controller (FLEXCOM)
  3. 34.9 TWI Functional Description
  4. 34.9.6 TWI FIFOs
  5. 34.9.6.7 TWI Single Data Access
Previous | Next

  • Description
  • Features
  • 1 Block Diagram
  • 2 Configuration Summary
  • 3 Package and Pinout
  • 4 Power Supply and Power Control
  • 5 Input/Output Lines
  • 6 Core and Interconnect
  • 7 Product Mapping and Peripheral Access
  • 8 Memories
  • 9 Safety and Security Features
  • 10 Real-Time Event Management
  • 11 Peripherals
  • 12 Cortex-M4 Processor (Arm)
  • 13 Flash Programming, Debug and Test Features
  • 14 ROM Code and Boot Strategies
  • 15 Supply Controller (SUPC)
  • 16 Reset Controller (RSTC)
  • 17 System Controller Write Protection (SYSCWP)
  • 18 Dual Watchdog Timer (DWDT)
  • 19 Clock Generator
  • 20 Power Management Controller (PMC)
  • 21 Parallel Input/Output Controller (PIO)
  • 22 Real-Time Clock (RTC)
  • 23 Real-time Timer (RTT)
  • 24 General Purpose Backup Registers (GPBR)
  • 25 Special Function Registers (SFR)
  • 26 Special Function Registers Backup (SFRBU)
  • 27 Bus Matrix (MATRIX)
  • 28 Chip Identifier (CHIPID)
  • 29 Secure Embedded Flash Controller (SEFC)
  • 30 Interprocessor Communication (IPC)
  • 31 Memory to Memory (MEM2MEM)
  • 32 Peripheral DMA Controller (PDC)
  • 33 Cortex-M Cache Controller (CMCC)
  • 34 Flexible Serial Communication Controller (FLEXCOM)
    • 34.1 Description
    • 34.2 Embedded Characteristics
    • 34.3 Block Diagram
    • 34.4 I/O Lines Description
    • 34.5 Product Dependencies
    • 34.6 Register Accesses
    • 34.7 USART Functional Description
    • 34.8 SPI Functional Description
    • 34.9 TWI Functional Description
      • 34.9.1 Transfer Format
      • 34.9.2 Modes of Operation
      • 34.9.3 Host Mode
      • 34.9.4 Multi-Host Mode
      • 34.9.5 Client Mode
      • 34.9.6 TWI FIFOs
        • 34.9.6.1 Overview
        • 34.9.6.2 Sending Data with FIFO Enabled
        • 34.9.6.3 Receiving Data with FIFO Enabled
        • 34.9.6.4 Sending/Receiving with FIFO Enabled in Client Mode
        • 34.9.6.5 Clearing/Flushing FIFOs
        • 34.9.6.6 TXRDY and RXRDY Behavior
        • 34.9.6.7 TWI Single Data Access
        • 34.9.6.8 TWI Multiple Data Access
        • 34.9.6.9 Transmit FIFO Lock
        • 34.9.6.10 FIFO Pointer Error
        • 34.9.6.11 FIFO Thresholds
        • 34.9.6.12 FIFO Flags
      • 34.9.7 TWI Comparison Function on Received Character
      • 34.9.8 Sniffer Mode
      • 34.9.9 TWI Register Write Protection
    • 34.10 Register Summary
  • 35 Quad Serial Peripheral Interface (QSPI)
  • 36 Segment LCD Controller (SLCDC)
  • 37 Timer Counter (TC)
  • 38 Analog-to-Digital Converter (ADC) Controller
  • 39 Analog Comparator Controller (ACC)
  • 40 Advanced Encryption Standard (AES)
  • 41 Advanced Encryption Standard Bridge (AESB)
  • 42 Secure Hash Algorithm (SHA)
  • 43 True Random Number Generator (TRNG)
  • 44 Integrity Check Monitor (ICM)
  • 45 Classical Public Key Cryptography Controller (CPKCC)
  • 46 Energy Metering Analog Front End (EMAFE)
  • 47 Multi Channel Serial Peripheral Interface (MCSPI)
  • 48 Pulse Width Modulation Controller (PWM)
  • 49 Universal Asynchronous Receiver Transmitter (UART)
  • 50 Electrical Characteristics
  • 51 Mechanical Characteristics
  • 52 Marking
  • 53 Ordering Information
  • 54 Revision History
  • 55 Product Identification System
  • Microchip Information

34.9.6.7 TWI Single Data Access

When FIFO is enabled and a byte access is performed in FLEX_TWI_THR, one byte is written in the FIFO. The same behavior applies for FLEX_TWI_RHR.

See TWI Transmit Holding Register and TWI Receive Holding Register.

However, it is possible to write/read multiple data each time FLEX_THR_THR/FLEX_US_RHR is accessed. See TWI Multiple Data Access.

The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.

About

Company
Careers
Contact Us
Media Center
Investor Relations
Corporate Responsibility

Support

Microchip Forums
AVR Freaks
Design Help
Technical Support
Export Control Data
PCNs

Quick Links

microchipDIRECT.com
Microchip University
myMicrochip
Blogs
Reference Designs
Parametric Search
Microchip Logo

Microchip Technology Inc.

2355 West Chandler Blvd.

Chandler, Arizona, USA

Microchip Facebook
Microchip LinkedIn
Microchip Twitter
Microchip Instagram
Microchip Weibo

© Copyright 1998-2024 Microchip Technology Inc. All rights reserved. Shanghai ICP Recordal No.09049794

Terms Of Use
Privacy Notice
Legal
Your Privacy Choices California Consumer Privacy Act (CCPA) Opt-Out Icon