9.2 Design for Security
The device embeds peripherals with security features to prevent counterfeiting, to secure external communication, and to authenticate the system.
The table below provides the list of peripherals and an overview of their security function. For more information, refer to the section on each peripheral.
| Peripheral | Function | Description | Comments |
|---|---|---|---|
| Secure Boot | Trusted Code Authentication | Based on hardware accelerated cryptographic modules | Software + AES, SHA |
| Cortex-M4 MPU | Memory Protection Unit | AES/SHA | – |
| PIO | I/O Control/ Peripheral Access | When a peripheral is not selected (PIO-controlled), I/O lines have no access to the peripheral. | – |
| Classical Public Key Crypto Library (CPKCL) | Cryptography standards | Software ECC (Asymmetric key algorithm, elliptic curves) | Software library |
| Software RSA (Asymmetric key algorithm) | – | ||
| AES | Hardware-accelerated AES up to 256 bits | FIPS-compliant | |
| SHA | SHA up to 512 bits and HMAC-SHA | FIPS-compliant | |
| TRNG | Cryptography | True Random Number Generator | – |
| AES | Anti-tampering | Immediate clear of keys in case of external tamper event detection (if enabled) | – |
| AES, SHA | Reinforced security | Improved robustness against attack | – |
| Integrity check | User-configurable immediate stop on integrity error detection | When the security error status flag is set in the user interface, an integrity error has been detected. These errors can occur only under abnormal operating conditions (electromagnetic attacks, VDD glitches, etc.) | |
| AES, SHA, TC, ICM, TRNG | Software access monitoring and integrity check | Dedicated interrupt line for security event |
Non-maskable in the peripheral. When a security error status flag is set in the user interface, an interrupt is triggered. These errors can occur only under abnormal operating conditions (electromagnetic attacks, VDD glitches, etc.) |
| Flash | Security bit | Reinforced Security bit to disable JTAG access Secure area key storage | – |
| Flash, GPBR | HW Flash Erase signal | Flash memory array is erased prior to Security bit erase | – |
| SRAM content can be configured to be erased on ERASE pin activation | |||
| GPBR can be configured to be erased on ERASE pin activation | |||
| AES keys and QSPI scrambling keys are erased on ERASE pin activation | |||
| QSPI | Scrambling | On-the-fly zero-wait state or zero latency scrambling/unscrambling | – |