28.6 CSYNC Bit

All bits in the Timer2 SFRs are synchronized to F_OSC/4 by default, not the Timer2 input clock. As such, if the Timer2 input clock is not synchronized to F_OSC/4, it is possible for the Timer2 input clock to transition at the same time as the ON bit is set in software, which may cause undesirable behavior and glitches in the counter. Setting the CSYNC bit remedies this problem by synchronizing the ON bit to the Timer2 input clock instead of F_OSC/4. However, as this synchronization uses an edge of the TMR2 input clock, up to one input clock cycle will be consumed and not counted by the Timer2 when CSYNC is set. Conversely, clearing the CSYNC bit synchronizes the ON bit to F_OSC/4, which does not consume any clock edges, but has the previously stated risk of glitches.