23.4.1 VDDIOxCON
Note:
- Refer to the MVIO VDDIOx Low-Voltage Detect parameters in the "Electrical Specifications" chapter for more information.
- When the VDDIOx IO monitors have been disabled using the MODE bit, the associated system level interrupts (VDDIOxRDYIF and VDDIOxPORIF) will no longer function and should be disabled using the respective interrupt enable bits (VDDIOxRDYIE and VDDIOxPORIE).
- This bit will always read back as
'
0
' when the VDDIOx Low-Voltage detection is disabled (LVD =0b000
), and when the the VDDIOx voltage domain is not ready for use.
Name: | VDDIOxCON |
Address: | 0x010D |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
IOMON | LVDSTAT | RDY | HYS | LVD[3:0] | |||||
Access | R/W | R | R | R/W | R/W | R/W | R/W | R/W | |
Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit 7 – IOMON VDDIOx I/O Monitor Disable(2)
Value | Description |
---|---|
1 |
VDDIOx internal voltage monitor and POR circuitry are disabled. |
0 |
VDDIOx internal voltage monitor and POR circuitry are enabled. |
Bit 6 – LVDSTAT VDDIOx Low Voltage Detect Output(3)
Bit 5 – RDY VDDIOx Ready Status Flag
Value | Description |
---|---|
1 |
VDDIOx supply is within an acceptable range and this voltage domain is ready to use. |
0 |
VDDIOx supply is not within an acceptable range and this voltage domain is not ready to use. |
Bit 4 – HYS Hysteresis Disable for VDDIOx Low-Voltage Detect(1)
Value | Description |
---|---|
1 |
Hysteresis disabled for VDDIOx LVD Trip Point Circuitry |
0 |
Hysteresis enabled for VDDIOx LVD Trip Point Circuitry |
Bits 3:0 – LVD[3:0] VDDIOx Low-Voltage Detect Interrupt Trip Point Selection
Reset States: |
|