35.16 UART Baud Rate Generator

The Baud Rate Generator (BRG) is a 16-bit timer that is dedicated to the support of the UART operation. The UxBRG register pair determines the period of the free-running baud rate timer. The multiplier of the baud rate period is determined by the BRGS bit.

The high baud rate range (BRGS = 1) is intended to extend the baud rate range up to a faster rate when the desired baud rate is not possible otherwise, and to improve the baud rate resolution at high baud rates. Using the normal baud rate range (BRGS = 0) is recommended when the desired baud rate is achievable with either range.

Important: BRGS = 1 is not supported in the DALI mode.

Writing a new value to UxBRG causes the BRG timer to be reset (or cleared). This ensures that the BRG does not wait for a timer overflow before outputting the new baud rate.

If the system clock is changed during an active receive operation, a receive error or data loss may result. To avoid this problem, check the status of the RXIDL bit to make sure that the receive operation is Idle before changing the system clock. The following table contains formulas for determining the baud rate.
Table 35-2. Baud Rate Formulas
BRGS BRG/UART Mode Baud Rate Formula
1 High Rate Fosc/[4(UxBRG+1)]
0 Normal Rate Fosc/[16(UxBRG+1)]
The following example provides a sample calculation for determining the baud rate and baud rate error.

Baud Rate Error Calculation

For a device with Fosc of 16 MHz, desired baud rate of 9600, Asynchronous mode, and BRGS = 0.

D e s i r e d ⁢ B a u d ⁢ r a t e = F O S C 16 × ( U x B R G + 1 )

Solving for UxBRG:

U x B R G = F O S C 16 × D e s i r e d ⁢ ⁢ B a u d r a t e − 1
U x B R G = 16000000 16 × 9600 − 1
U x B R G = 103.17 ≃ 103
C a l c u l a t e d ⁢ B a u d ⁢ r a t e = 16000000 16 × ( 103 + 1 )
C a l c u l a t e d ⁢ B a u d ⁢ r a t e = 9615
E r r o r ⁢ =   C a l c u l a t e d ⁢ B a u d ⁢ r a t e − D e s i r e d B a u d r a t e D e s i r e d B a u d r a t e
E r r o r ⁢ =   9615 − 9600 9600
E r r o r ⁢ ≃   0.16 %