27.13.3 TxCLK

Timer Clock Source Selection Register
Name: TxCLK
Address: 0x317,0x328

Bit 76543210 
    CS[4:0] 
Access R/WR/WR/WR/WR/W 
Reset 00000 

Bits 4:0 – CS[4:0] Timer Clock Source Selection

Table 27-4. Timer Clock Sources
CS Clock Source
Timer1 Timer3
11111 - 10110 Reserved
10101 CLC8_OUT
10100 CLC7_OUT
10011 CLC6_OUT
10010 CLC5_OUT
10001 CLC4_OUT
10000 CLC3_OUT
01111 CLC2_OUT
01110 CLC1_OUT
01101 TMR3_OUT Reserved
01100 Reserved TMR1_OUT
01011 TMR0_OUT
01010 CLKREF_OUT
01001 EXTOSC
01000 SFINTOSC
00111 SOSC
00110 MFINTOSC (31.25 kHz)
00101 MFINTOSC (500 kHz)
00100 LFINTOSC
00011 HFINTOSC
00010 FOSC
00001 FOSC/4
00000 Pin selected by T1CKIPPS Pin selected by T3CKIPPS
Reset States: 
POR/BOR = 00000
All Other Resets = uuuuu