32.9.10 PWMxSaCFG

Note:

Changes to this register must be done only when the EN bit is cleared.

Name:

PWMxSaCFG

PWM Slice “a” Configuration Register⁽¹⁾


Bit	7	6	5	4	3	2	1	0
	POL2	POL1			PPEN	MODE[2:0]
Access	R/W	R/W			R/W	R/W	R/W	R/W
Reset	0	0			0	0	0	0

Bit 7 – POL2 PWM Slice “a” Parameter 2 Output Polarity

Value	Description
`1`	PWMx_SaP2_out is low true
`0`	PWMx_SaP2_out is high true

Bit 6 – POL1 PWM Slice “a” Parameter 1 Output Polarity

Value	Description
`1`	PWMx_SaP1_out is low true
`0`	PWMx_SaP1_out is high true

Bit 3 – PPEN Push-Pull Mode Enable

Each period the output alternates between PWMx_SaP1_out and PWMx_SaP2_out. Only Left and Right Aligned modes are supported. Other modes may exhibit unexpected results.

Value	Description
`1`	PWMx Slice “a” Push-Pull mode is enabled
`0`	PWMx Slice “a” Push-Pull mode is not enabled

Bits 2:0 – MODE[2:0] PWM Module Slice “a” Operating Mode Select

Selects operating mode for both PWMx_SaP1_out and PWMx_SaP2_out

Value	Description
`11x`	Reserved. Outputs go to Reset state.
`101`	Compare mode: Toggle PWMx_SaP1_out and PWMx_SaP2_out on PWM timer match with corresponding parameter register
`100`	Compare mode: Set PWMx_SaP1_out and PWMx_SaP2_out high on PWM timer match with corresponding parameter register
`011`	Variable Aligned mode
`010`	Center-Aligned mode
`001`	Right Aligned mode
`000`	Left Aligned mode

Changes to this register must be done only when the EN bit is cleared.