20.1.4 Interrupt-on-Change and DMA/ADC Triggers
All the Signal Routing Ports on this device support Interrupt-on-Change. The Interrupt-on-Change feature for PORTW is provided using the IOCWP, IOCWN and IOCWF registers. The logical OR of all the Interrupt-on-Change flags for all the Signal Routing Ports is available at the system-level as IOCV interrupt as shown in Figure 20-2 below. See the “IOC – Interrupt-on-Change” chapter for more information.
In addition to the Interrupt-on-Change, the output of each pin of the Signal Routing Port is also a trigger for the DMA and ADC as shown in the Figure 20-1. The IOCWP and IOCWN registers are used to select the edge of the output pin transition that generates a trigger.
- Select the edge that may trigger the DMA/ADC by setting the appropriate bit in the IOCWP and IOCWN registers. Setting IOCWPn bit enables positive edge trigger. Setting the IOCWNn bit enables negative edge trigger. Setting both IOCWPn and IOCWNn bits enable trigger on either edge.
- Select the “IOCWFn Flag” as the trigger source in the DMAnSIRQ, DMAnAIRQ, or ADACT registers as appropriate.