20.1.2 Signal Routing Port Input

The input to the Signal Routing Port is selected using the PORTWINx registers. There is a separate PORTWINx register for each pin of the Signal Routing Port. Several core independent peripherals are available as input selections to the multiplexer as shown in the PORTWINx Input Selections table below. In addition to the core independent peripherals, the following inputs are also added to each multiplexer:

  • The corresponding LATWn register bit – allows for software writes to the Signal Routing pin.
  • Input from the immediate next Signal Routing pin RW[n+1] – allows for shift register operation.
  • An external I/O pin – allows physical inputs.
As previously mentioned, one of the input selections available to the PORTWINx register is the LATWn register bit. The LATW register allows the user to write a value to the Signal Routing Port from software. Unlike a typical I/O port, LATW is a separate register from the actual data register as shown in Figure 20-1 block diagram.
Important:
  1. To perform a software write to one of the Signal Routing pins using the LATW register, the PORTWINx register for that Signal Routing pin must select the corresponding LATWn bit as input to the Signal Routing Port.
  2. Reading the LATW register returns the most recently written value to the LATW register and not the actual input to the Signal Routing Port. The actual input to the Signal Routing Port is selected using PORTWINx register and can be read using the PORTW register. This is similar to the standard I/O pins read/write operations.

The following input selection multiplexers are available on this device:

Table 20-1. PORTWINx Input Selections
IN[3:0] PORTWIN0 PORTWIN1 PORTWIN2 PORTWIN3 PORTWIN4 PORTWIN5 PORTWIN6 PORTWIN7
1111-1101 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
1100 TU16A_OUT TU16B_OUT TMR2_OUT TMR6_OUT TU16A_OUT TU16B_OUT TMR4_OUT TMR6_OUT
1011 SPI2_SS SPI2_SDO SPI2_SCK SPI2_SS SPI2_SDO SPI2_SCK SPI2_SDO SPI2_SCK
1010 CLKREF_OUT NCO1_OUT CLKREF_OUT NCO1_OUT CLKREF_OUT NCO1_OUT CLKREF_OUT NCO1_OUT
1001 HLVD_OUT ZCD1_OUT HLVD_OUT ZCD2_OUT HLVD_OUT ZCD1_OUT HLVD_OUT ZCD2_OUT
1000 CLC1_OUT CLC2_OUT CLC3_OUT CLC4_OUT CLC5_OUT CLC6_OUT CLC7_OUT CLC8_OUT
0111 CCP1_OUT PWM1S1P1_OUT PWM2S1P1_OUT PWM3S1P1_OUT CCP2_OUT PWM1S1P2_OUT PWM2S1P2_OUT PWM3S1P2_OUT
0110 CMP1_OUT CMP2_OUT CMP1_OUT CMP2_OUT CMP1_OUT CMP2_OUT CMP1_OUT CMP2_OUT
0101 SPI1_SS SPI1_SDO SPI1_SCK SPI1_SS SPI1_SDO SPI1_SCK SPI1_SDO SPI1_SCK
0100 TU16A_OUT TU16B_OUT TMR2_OUT TMR4_OUT TU16A_OUT TU16B_OUT TMR2_OUT TMR4_OUT
0011 PORTWIN0PPS PORTWIN1PPS PORTWIN0PPS PORTWIN1PPS PORTWIN0PPS PORTWIN1PPS PORTWIN0PPS PORTWIN1PPS
0010 RC0 RC1 RC2 RC3 RC4 RC5 RC6 —
0001 RW1 RW2 RW3 RW4 RW5 RW6 RW7 RW0
0000 LATW0 LATW1 LATW2 LATW3 LATW4 LATW5 LATW6 LATW7