The MVIO module has three top level system interrupts in the PIRx registers. An interrupt
request is generated when the corresponding interrupt source has been enabled and when
the interrupt flag is set. The interrupt request remains active until the interrupt flag
has been cleared in hardware when the interrupt condition is no longer met. Refer to the
“VIC - Vectored Interrupt Controller Module” chapter for more
information.
These system level interrupts also act as DMA triggers. The interrupt does not need to be
enabled to be used as a trigger for DMA transfers. Refer to section “Types of
Hardware Triggers” in the “DMA – Direct Memory Access” chapter for more
information on how to use these DMA triggers.
When a V
DDIOx Power-on Reset (POR) is detected by the MVIO module, the
VDDIOxPORIF of the PIRx register will set signifying that V
DDIOx has entered
a POR state. VDDIOxPORIF will remain high as long as the V
DDIOx domain is in
a POR state. Once the voltage domain is released from POR, VDDIOxPORIF will be cleared
in hardware. This system level interrupt can be enabled or disabled by writing to the
VDDIOxPORIE bit in the PIEx register.
Important: VDDIOxPORIF is a level sensitive interrupt, not edge
sensitive. This interrupt flag cannot be cleared and will remain high as long as the
VDDIOx voltage domain is held in a POR state.
The
VDDIOxRDYIF interrupt flag of the PIRx register is used to
monitor the status of the respective V
DDIOx power domain. The
VDDIOxRDYIF will be set when the integrated I/O monitor
circuitry detects that the MVIO supply does not meet or exceed the minimum specified
voltage requirements for the module to operate properly. Once the integrated I/O voltage
monitors detect that the V
DDIOx domains are fully powered up and that the
proper voltage level thresholds are being met for the MVIO module to function properly,
the
VDDIOxRDYIF interrupt flag will be cleared in hardware.
This system level interrupt can be enabled or disabled by writing to the VDDIOxRDYIE bit
in the PIEx register.
Important: VDDIOxRDYIF is a level sensitive interrupt, not edge
sensitive. VDDIOxRDYIF cannot be cleared and will remain
high as long as the VDDIOx supply voltage is below the minimum specified
voltage requirements for the module to operate properly.
The
RDY bit of VDDIOxCON is a logical OR of the VDDIOxPORIF and VDDIOxRDYIF
and can be used to monitor the status of the MVIO module voltage supply in software.
When the V
DDIOx Low-Voltage detection circuit is enabled using the
LVD
selection bits, and the corresponding V
DDIOx supply voltage drops below the
configured LVD threshold during normal operation, the VDDIOxLVDIF of the PIRx register
will be set. Once the V
DDIOx supply voltage recovers and is no longer lower
than the LVD threshold, the VDDIOxLVDIF will be cleared in hardware. This system level
interrupt can be enabled or disabled by writing to the VDDIOxLVDIE bit in the PIEx
register. The
LVDSTAT bit of VDDIOxCON represents the VDDIOxLVDIF and can be used to monitor the status of
the LVD detection circuitry in software.
Important: The
VDDIOx LVD Interrupt is level sensitive, not edge sensitive.
VDDIOxLVDIF cannot be cleared as long as the VDDIOx supply voltage is
below the configured LVD threshold.
Since the MVIO system level interrupts are level sensitive, once an interrupt has
occurred, the corresponding interrupt enable bit should be cleared to prevent the CPU
from continuously jumping into the same Interrupt Service Routine repeatedly. The
corresponding status bits can be monitored in software to determine when the
VDDIOx supply has recovered from either event after which the system
level interrupt should then be re-enabled.
