14.13.3 PCON1
| Name: | PCON1 |
| Address: | 0x4F1 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| PORVDDIO2 | RVREG | MEMV | RCM | ||||||
| Access | R/W/HC | R/W/HC | R/W/HC | R/W/HC | |||||
| Reset | 0 | 1 | 0 | q |
Bit 3 – PORVDDIO2 VDDIO2 Power-on Reset Flag
| Reset States: |
|
| Value | Description |
|---|---|
| 1 | No
VDDIO2 Power-on Reset occurred or set to ‘1’
by firmware |
| 0 | A
VDDIO2 Power-on Reset occurred (set to ‘0’
in hardware when a VDDIO2 Power-on Reset
occurs) |
Bit 2 – RVREG Main LDO Voltage Regulator Reset Flag
| Reset States: |
|
| Value | Description |
|---|---|
| 1 | No LDO
or ULP “ready” Reset has occurred or set to ‘1’ by
firmware |
| 0 | LDO or ULP “ready” Reset has occurred (VDDCORE reached its minimum spec) |
Bit 1 – MEMV Memory Violation Reset Flag
| Reset States: |
|
| Value | Description |
|---|---|
| 1 | No
memory violation Reset occurred or set to ‘1’ by
firmware |
| 0 | A
memory violation Reset occurred (set to ‘0’ in hardware
when a Memory Violation occurs) |
Bit 0 – RCM Configuration Memory Reset Flag
| Reset States: |
|
| Value | Description |
|---|---|
| 1 | A Reset occurred due to corruption of the configuration and/or calibration data latches |
| 0 | The configuration and calibration latches have not been corrupted |