10.2 Gigabit Ethernet PHY

The SAM9X75 SOM Series embeds one low-power, single port, triple speed (10BASE-T/100BASE-TX/1000BASE-T) Ethernet physical layer transceiver (PHY) LAN8840 optimized for precision process timing.

The LAN8840T-V/PSA supports industry-standard RGMII (Reduced Gigabit Media Independent Interface) providing chip-to-chip connection to a host device with an integrated Gigabit Ethernet MAC.

The device is available in a 7x7 mm 48-pin VQFN package and is implemented in the system as shown in the figure below.

For more information, refer to the Ethernet PHY LAN8840 data sheet (see Reference Documents).

Figure 10-1. Ethernet PHY Digital/Analog Block Diagram
The SAM9X75 SOM Series embeds straps on the MODE[4:0] signals of the LAN8840 pins (PB0, PB1, PB8, PB11, PB12) to ensure that a set of features is configured automatically when the GMAC_NRST signal (pin 43) is released. The default settings are as follows:
  • Auto-negotiation to automatically select the highest link-up speed and duplex: Enabled.
  • Automatic MDI/MDI-X crossover to detect and correct pair swapping at all operating speeds: Enabled.
  • Energy Efficient Ethernet (EEE) support: Enabled.
  • Single port with triple speed (10BASE-T/100BASE-TX/1000BASE-T) link in full duplex modes: Enabled.
The LAN8840 PHY is not fully configured. Configuration straps (pull-up/down resistors) on the GMAC_LEDx pads (pins 44, 45, 46, 47 and 48) must be placed outside the module and GMAC_NRST (pin 43) can be connected as follows:
  • The GMAC_LED5_ALLPHYAD pad (pin 44) allows the use of any value on the GMAC_LEDx_PHYAD[2:0] pads (pins 46, 47, 48), or 0 by default. This pin can be pulled up or down externally.
  • The GMAC_LEDx_PHYAD[2:0] pads (pins 46, 47, 48) are used to set the PHY address.
  • The GMAC_NRST pad can be connected to the global NRST signal (pin 77) or to any system reset management.
Note: Any required external pulling configuration strap must be tied to either VDD_3V3 or GND, depending on customer needs. For more details, refer to the LAN8840 data sheet (see Reference Documents).
The LAN8840 PHY is supplied by:
  • VDD_3V3 for digital interfacing with the SAM9X75 SiP device,
  • VDD_1V15_ETH for the LAN8840 digital PLL and analog interfacing with the outside world.

Both are delivered by the MCP16502 PMIC.