9.2 Physical Memory Map

The high-speed bus is implemented as a bus matrix. All high-speed bus addresses are fixed, and they are never remapped in any way, even during boot. The 32-bit physical address space is mapped as follows:

Table 9-1. Physical Memory Map
Memory	Start Address	Size in KB (unless otherwise stated)
Memory	Start Address	SAMD51x20 SAME51x20 SAME53x20 SAME54x20	SAMD51x19 SAME51x19 SAME53x19 SAME54x19	SAMD51x18 SAME51x18 SAME53x18
Embedded Flash	0x00000000	1024	512	256
Embedded SRAM	0x20000000	256	192	128
Peripheral Bridge A	0x40000000	16384 Bytes
Peripheral Bridge B	0x41000000
Peripheral Bridge C	0x42000000
Peripheral Bridge D	0x43000000
Backup SRAM	0x47000000	8
NVM User Row	0x00804000	512 Bytes

Note:

X = G, J, N or P. Refer to Ordering Information for available device part numbers.