56.3 Maximum Clock Frequencies (125°C)

Table 56-2. Maximum Peripheral Clock Frequencies⁽¹⁾
Symbol	Description	Max.	Units
f_CPU	CPU clock frequency	100	MHz
f_AHB	AHB clock frequency	100	MHz
f_{APBx, x = {A, B, C, D}}	APBA, APBB, APBC and APBD clock frequency	100	MHz
f_{GCLK_EIC}	EIC input clock frequency	90	MHz
f_{GCLK_FREQM_MSR}	FREQM Measure	180	MHz
f_{GCLK_FREQM_REF}	FREQM Reference	90	MHz
f_{GCLK_EVSYS_CHANNEL_x, x = {0,.., 11}}	EVSYS channel ‘x’ input clock frequency	90	MHz
f_{GCLK_SERCOMx_CORE, x = {0, ... , 7}}	SERCOMx input clock frequency	90	MHz
f_{GCLK_CANx, x = {0, 1}}	CANx input clock frequency	90	MHz
f_{GCLK_I2S}	I²S input clock frequency	90	MHz
f_{GCLK_SDHCx_CORE, x = {0, 1}}	SDHCx input clock frequency	150	MHz
f_{GCLK_TCCx, x = {0, ... , 4}}	TCCx input clock frequency	180	MHz
f_{GCLK_TCx, x = {0, ... , 3}}	TC0, TC1, TC2, TC3 input clock frequency	180	MHz
f_{GCLK_PDEC}	PDEC input clock frequency	180	MHz
f_{GCLK_CCL}	CCL input clock frequency	90	MHz
f_{GCLK_CM4_TRACE}	CM4 Trace input clock frequency	100	MHz
f_{GCLK_AC}	AC digital input clock frequency	90	MHz
f_{GCLK_ADCx, x = {0, 1}}	ADCx input clock frequency	90	MHz
f_{GCLK_DAC}	DAC input clock frequency	90	MHz

Note:

These values are based on simulation. They are not covered by production test limits or characterization.