10.3.2 Configuration

Figure 10-1. Host-Client Relations High-Speed Bus Matrix
Table 10-2. High-Speed Bus Matrix Hosts
High-Speed Bus Matrix HostsHost ID
CM4S - Cortex M4 Processor0
CMCC - Cortex-M Cache Controller

(Cortex-M4F ICode and DCode Interfaces)

1
DMAC - Direct Memory Access Controller/Data Write Access4
DMAC - Direct Memory Access Controller/Data Read Access5
ICM - Integrity Check Monitor6
DSU - Device Service Unit7
Table 10-3. High-Speed Bus Matrix Clients
High-Speed Bus Matrix ClientsClient ID
Internal Flash Memory0, 1
SmartEEPROM2
SRAM Port 0 - CM4 Access3
SRAM Port 1 - DSU Access4
SRAM Port 2 - DMAC Data-Write Access5
SRAM Port 3 - DMAC Data-Read and ICM Access6
AHB-APB Bridge A7
AHB-APB Bridge B8
AHB-APB Bridge C9
AHB-APB Bridge D10
PUKCC11
SDHC012
SDHC113
QSPI14
BACKUP RAM Memory15