2.3.1 CAN Source Clock
If the UPB clock is less than or equal to the CAN clock, it is going to have impact on some functionalities of CAN-FD.
Work Around
The CAN source clock must be less than the CAN UPB/peripheral clock (PB2_CLK). Select ETHPLL as the CAN source clock and configure CFGCON0.CANFDDIV such that the CAN source clock (ETHPLL) is less than PB2_CLK(CAN UPB/peripheral clock).
Affected Silicon Revisions
| A0 | A1 | B0 | C0 |
|---|---|---|---|
| X | X | X | X |