1 Silicon Errata Summary
| Module | Feature | Issue Summary | Affected Revisions | |||
|---|---|---|---|---|---|---|
| A0 | A1 | B0 | C0 | |||
| Capacitive Voltage Divider (CVD) Controller | CVD Event | An invalid CVD event can occur while the FIFO counter increments. | X | X | X | X |
| Controller Area Network (CAN) | Interrupt | The CAN Wake Interrupt Flag bit, WAKIF, is set even when the CAN module is disabled. | X | X | X | X |
| Controller Area Network (CAN) | Controller Area Network (CAN ) First-In, First-Out (FIFO) | The CAN FIFO abort operation during transmission does not set the TXABAT bit in FIFOCON register. | X | X | X | X |
| Controller Area Network - Flexible Data-Rate (CAN-FD) | CAN Source Clock | Certain features of the CAN-FD cannot operate optimally if the UPB Clock’s speed is equal to or less than that of the CAN clock. | X | X | X | X |
| In-Circuit Serial Programming™ (ICSP™) | Test Data Out (TDO) | The TDO pin becomes an output and toggles while programming on any ICSP™ PGECx/PGEDx pair. | — | X | X | X |
| Inter-Integrated Circuit (I2C) | I2C Client | The 7-bit address that matches the 10-bit upper address value (111_10xx_xxx) is not accepted regardless of the STRICT bit setting. | X | X | X | X |
| Non-Volatile Memory (NVM) | Self Erase and Self Program | PIC32MZ2051W104132/WFI32E03/WFI32E04 may generate an invalid instruction exception while performing run-time self-erase and-self program operations. | X | — | — | — |
| Non-Volatile Memory (NVM) | NVM Read Operation | PIC32MZ1025W104132/WFI32E01/WFI32E02 may require additional recovery time after Deep Sleep mode or require time after NVM program/erase to next read operation. | — | X | X | X |
| Power | Low-power Mode | Excess leakage current observed in some devices under certain voltage and temperature ranges when the USB controller is disabled and not connected. | — | X | X | — |
| Power | Low-power Mode | The system does not enter the Sleep mode or Deep Sleep mode or
Extreme Deep Sleep mode when the Flash power-down (NVM- CON2.SLEEP =
0) bit is disabled and the system is operating at
less than 35 MHz. | X | — | — | — |
| Peripheral Trigger Generator (PTG) | PTG Software Trigger (PTGSWT) Bit | The hardware does not clear the PTGSWT bit in case of back-to-back
execution of the SWTRGE command. | X | X | X | X |
| Peripheral Trigger Generator (PTG) | PTG Start (PTGSTRT) Bit | PTGSTRT is not cleared when PTGON = 0. | X | X | X | X |
| Serial Peripheral Interface (SPI) | Block Transmission | The SRMT bit incorrectly indicates the end of transmission for the last PBCLK. | X | X | X | X |
| Timer1 | Asynchronous Counter | Timer1 in Asynchronous External Counter mode does not reflect the first count from an external T1CLK input. | X | X | X | X |
| Timer1 | Timer1 Register (TMR1) | The TMR1 register of Timer1 in Asynchronous mode remains at the initial set value for five external clock pulses after wake-up from Sleep mode. | X | X |
X | X |
| Timer1 | Asynchronous Mode | Timer1 counts beyond the period value in Asynchronous mode when the period is 0x01. | X | X | X | X |
| Universal Asynchronous Receiver Transmitter (UART) | TX/RX Interrupt | A UART Transmit Interrupt (UTXI- SEL[1:0] bits (UxSTA[15:14]) =
‘0b00) is generated and asserted while the transmit
buffer contains at least one empty space and the UART Receiver Interrupt
Flag bit (URXISEL[1:0] bits (UxSTA[7:6]) = ‘0b00) is
asserted while the receive buffer is not empty and
non-functional. | X | X | X | X |
| Universal Asynchronous Receiver Transmitter (UART) | TX Interrupt | A UART Transmit Interrupt (UTXI- SEL[1:0] bits =
‘0b01) is generated but does not remain asserted
after all of the characters are transmitted. | X | X | X | X |
| Universal Asynchronous Receiver Transmitter (UART) | TX Interrupt | A UART Transmit Interrupt (UTXI- SEL[1:0]bits =
‘0b10) is generated but does not remain asserted
while the transmit buffer is empty. | X | X | X | X |
| Universal Asynchronous Receiver Transmitter (UART) | RX Interrupt | The UART Receive Interrupt flag (URXISEL[1:0] bits =
‘0b01) is asserted only when the receive buffer
equals one-half full and not when the receive buffer is greater than
one-half full. | X | X | X | X |
| Universal Asynchronous Receiver Transmitter (UART) | RX Interrupt | The UART Receive Interrupt Flag bit (URXISEL[1:0] bits =
‘0b10) is asserted only when the receive buffer
equals three-quarters full and not when the receive buffer is greater
than three-quarters full. | X | X | X | X |
| Universal Serial Bus (USB) | Compliance | SE0 output of the USB peripheral may not meet compliance requirements. | — | X | X | — |
| Watchdog Timer (WDT) | WDT Reset | WDT does not reset the CPU within the expected time period across the voltage and temperature ranges. | — | X | — | — |
| Wi-Fi® | Data Transmission | Degraded TX EVM is observed during low Wi-Fi® traffic with a long idle duration between packet transmission. | — | X | — | — |
| Wi-Fi® | Wi-Fi® | Potential issue where the DMA interface module can latch the sub-MSDU length for an A-MSDU from the header as a frame is received but before the FCS is validated, resulting in the possibility of subsequent valid frames being dropped. | — | X | — | — |