3.4.1 Chip Erase

On the dsPIC33A, the impact of a chip erase operation through the ICSP interface has different implications based on the device configuration.

When UCB is not erase or write locked, a chip erase will erase the entire device, including all IRT and OTP sections. This allows for erasing the device during the development cycle.

When UCB is write or erase locked, a chip erase will not erase OTP or IRT sections.

A chip erase operation will always erase the UCA section, which includes code protection. This can be used to create IRT and OTP sections that are kept through an erase/program cycle. This can be used as a mechanism to provide a secure local update mechanism as described by Section 3.5.3 of the NIST SP 800-193 specification, if there is physical security of the device.

To completely block chip erases, the ICSP™ Write Inhibit feature can be used to disable all external erase/write operations through the ISCP interface.