3 Results

The following table lists the interrupt latency measurement results.

Table 3-1. Interrupt Latency Measurement Results
Interrupt Type	Interrupt Latency
Global	37 core clock cycles
Local	30 core clock cycles
CLINT Software Interrupt	16 core clock cycles

Note: Software CLINT latency is generated in u54_1 core and handled in mtrap function.

Table 3-2. Data Transfer Throughput Between LIM and Fabric LSRAM using MSS PDMA
Transfer Size in Bytes	LSRAM to LIM		LIM to LSRAM
Transfer Size in Bytes	Core Clock Cycles	Mbits/Seconds	Core Clock Cycles	Mbits/Seconds
1 Kbyte	965	5350.052	1061	4862.298
4 Kbytes	3439	5969.105	3683	5572.789
8 Kbytes	6743	6081.663	7169	5719.872
16 Kbytes	13363	6134.032	14165	5786.537
32 Kbytes	26521	6179.61	28129	5826.251
64 Kbytes	52933	6191.403	56033	5848.817
128 Kbytes	105719	6199.544	112009	5851.376
256 Kbytes	211439	6199.28	223789	5857.155

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