Introduction

Microchip's PolarFire® SoC FPGAs include the industry's RISC-V based Microprocessor Subsystem (MSS) and FPGA fabric that inherits all the features of the PolarFire family. The PolarFire SoC MSS includes 5x 64-bit RISC-V processor cores, AXI switch, DDR controller, Fabric Interface Controllers (FIC), and a rich set of peripherals. It also offers an unparalleled combination of low power consumption, thermal efficiency, and defense-grade security for smart, connected systems. It is the first SoC FPGA with a deterministic L2 memory subsystem enabling real-time applications. Built on the award-winning, mid-range, low-power PolarFire FPGA architecture, PolarFire SoC devices deliver up to 50% lower power than alternative FPGAs, span from 25k to 460k logic elements, and feature 12.7G transceivers.

Microchip's PolarFire SoC Icicle kit features an MPFS250T PolarFire SoC device and on- board memories such as LPDDR4, SPI, and eMMC flash for running Linux. For more information, see the UG0882: PolarFire SoC FPGA ICICLE Kit User Guide.

The following measurements are performed on PolarFire SoC FPGA:

  • Interrupt latency difference between Global and Local interrupts.
  • Data transfer throughput is measured from LIM to Fabric LSRAM and Fabric LSRAM to LIM.

Interrupt latency refers to the delay between the start of an Interrupt and the detection of the interrupt by the processor in the application. The interrupt latency is expressed in processor clock cycles. Latency measurement is carried out and compared between Local interrupt and Global interrupt using the Bare metal application. Local interrupts are signaled directly to an individual hart with a dedicated interrupt value. This allows for reduced interrupt latency. Global interrupts by contrast, are routed through a Platform-Level Interrupt Controller (PLIC), which can direct interrupts to any hart in the system through the external interrupt.

For more information, see the PolarFire SoC FPGA MSS Technical Reference Manual.

The interrupt latency and the data transfer throughput are measured using the PolarFire SoC FPGA Icicle kit. The following table lists the configuration used for the measurements.

Table . System Configuration
System ConfigurationDescription
DevicePolarFire SoC FPGA, RISC-V 64-bit
ApplicationBare Metal
CPU Core Frequency625 MHz
CompilerRISC-V GCC
Target Processorriscv64
Tool ChainSoftConsole v2021.1
SoftConsole Tool Optimization Level

None is used for interrupt latency measurement.

Optimize fast (-Ofast) is used for data transfer throughput measurement between LIM and Fabric LSRAM.
MPFS-HALVersion 1.8.117
Linker Script SettingsInstruction Tightly Integrated Memory (ITIM) used for the code section.

Scratchpad is used for the stack.

FIC and Fabric Frequency200 MHz
Interrupt Lines UsedMSS_INT_F2M0 (Local) and MSS_INT_F2M1 (Global)