2 Data Transfers Throughput between LIM and FPGA Fabric LSRAM

Figure 2-1 shows the block diagram for measuring the throughput for data transfers between LIM and fabric LSRAM. LSRAM block is connected to the MSS using the FIC0 interface. The core complex Direct Memory Access (DMA) is used for data transfers between LIM and LSRAM, and throughput is measured. To achieve this, the PDMA driver is added to the Bare Metal application and configured with required registers. See Table 2-1 for fabric LSRAM and LIM address map.

Implementation

To perform LSRAM to LIM data transfer, the fabric LSRAM is initialized by the application core (U54_1), with an incremental data pattern. Core complex DMA is initialized by declaring DMA channel and configured by writing to the channel registers —source address (LSRAM), destination address (LIM), and number of bytes to transfer. The DMA transfer is initiated using setup transfer and start DMA transfer functions. DMA transfer complete status is checked, then the LIM data is read and verified.

To perform LIM to LSRAM data transfer, the source address is replaced with the destination address and vice-versa. The same process as described in preceding paragraph is repeated.

For measuring the data transfer throughput, CSR mcycle is read before DMA transfer and after the DMA transfer completion. The time difference between mcycle read values are used to convert into bits/seconds.