The PIC18F04/05/14/15Q40 devices you have received conform functionally to the current device data sheet (DS40002236C), except for the anomalies described in this document.
The silicon issues discussed in the following pages are for silicon revisions with the Device and Revision IDs listed in the table below.
The errata described in this document will be addressed in future revisions of the PIC18F04/05/14/15Q40 silicon.
Note: This document summarizes all silicon errata issues
from all revisions of silicon, previous as well as current.
| Part Number | Device ID | Revision ID | ||
|---|---|---|---|---|
| D1 | D3 | E0 | ||
| PIC18F04Q40 | 0x7640 | 0xA0C1 | 0xA0C3 | 0xA0D0 |
| PIC18F05Q40 | 0x7600 | 0xA0C1 | 0xA0C3 | 0xA0D0 |
| PIC18F14Q40 | 0x7620 | 0xA0C1 | 0xA0C3 | 0xA0D0 |
| PIC18F15Q40 | 0x75E0 | 0xA0C1 | 0xA0C3 | 0xA0D0 |
Important: Refer to the Device/Revision ID section
in the current “PIC18FXXQ40 Family Programming Specification” (DS40002185) for more
detailed information on Device Identification and Revision IDs for your specific
device.
| Module | Feature | Item No. | Issue Summary | Affected Revisions | ||
|---|---|---|---|---|---|---|
| D1 | D3 | E0 | ||||
| Analog-to-Digital Converter with Computation | ADCC | 1.1.1 | Double Sample Conversions | X | X | |
| Electrical Specifications | ADC Offset Error | 1.2.1 | ADC Offset Error specification lowered in ECH, ECM and ECL modes | X | ||
| I2C | I2C | 1.3.1 | I2C Start and/or Stop flags may be set When I2C is enabled | X | ||
| 1.3.2 | MDR bit is not cleared after Bus Timeout | X | X | X | ||
| 1.3.3 | Bus Timeout not detected properly when External Host Clock stretches | X | X | X | ||
| 1.3.4 | Clock Stretch Disable not working properly | X | X | X | ||
| 1.3.5 | Bus Timeout causes false Start/Stop | X | X | X | ||
| Universal Asynchronous Receiver Transmitter | UART | 1.4.1 | UART TXDE signal may go low before the STOP bit has been entirely transmitted. | X | X | X |
| 1.4.2 | Asynchronous 9-bit UART Address mode address mismatch | X | X | |||
| Signal Measurement TImer | SMT | 1.5.1 | Reset Bit | X | X | |
| PIC18 CPU | FSR Shadow Registers | 1.6.1 | FSR Shadow Registers are not writable | X | X | |
| ICSP™ | Low-Voltage Programming (LVP) | 1.7.1 | Low Voltage Programming is not possible when VDD is below BORV while BOR is enabled. | X | X | X |
|
Note: Only those issues
indicated in the last column apply to the current silicon revision.
|
||||||