The figure below depicts MCP16502 power management.
The MCP16502 is a Fast mode Plus device, supporting data transfers at up to 1 Mbit/s as described in the I2C Bus specification. The MCP16502 is a slave-only device without clock stretching capability. The MCP16502 assumes that the I2C logic levels on the bus are generated by a device operating from a nominal supply voltage of 3.3V (with ±10% tolerance). This is typically the I/O voltage generated by Buck1 (VDDIO). Therefore, VIH and VIL are not related to the SVIN voltage value. The SDA and SCL lines should not be pulled up to the MCP16502 SVIN voltage, but to the I2C master interface supply voltage (3.3V nominal). The MCP16502 I2C interface is always accessible, even in the OFF state, as long as the SVIN pin is powered. In the OFF state, the VDDIO voltage from Buck1 is turned off and therefore the I2C pull-up rail must be provided externally.
For more information, refer to the PMIC MCP16502 data sheet.
| PIO | Mnemonic | Shared PIO | Signal Description |
|---|---|---|---|
| PIOBU7 | LPM | – | Low-Power mode input pin. In combination with PWRHLD and HPM, this pin defines the power mode status of the MCP16502. |
| PC31 | HPM | – | High-Performance mode input pin. In combination with PWRHLD and LPM, this pin defines the power mode status of the MCP16502. |
| SHDN | PWRHLD | – | Power hold input. Typically asserted high by the MPU to maintain power after the initial startup triggered by nSTRT. PWRHLD will be asserted low by the MPU to initiate a PMIC shutdown sequence. |
| PB_NSTRT | nSTRT | – | Start event input. Drive nSTRT low to initiate a start-up sequence. nSTRT is internally pulled up. |
| PB18 | nINT0 | – | Active low, open-drain interrupt output |
| NRST | nRSTO | NRST | Active low, open-drain reset output |
| PC28 | TWD | POWER TWI | TWI interface serial data |
| PC29 | TWCK | POWER TWI | TWI interface serial clock |