External Chip Reset

When the Reset push button switch is pressed, the device places all pins into their default state. An additional PIO (PB16) allows the LAN9252 to be reset by software.

The figure below illustrates the implementation of the EtherCAT interface.

Figure 1. EtherCAT Interface

The table below shows the signal assignment on the HBI interface between SAMA5D27 and LAN9252.

Table 1. EBI Signal Description
PIO Mnemonic Shared Signal Description
PA22 D0 WILC3000 Data
PA23 D1 Data
PA24 D2 Data
PA25 D3 Data
PA26 D4 Data
PA27 D5 Data
PA28 D6 WILC3000 Data
PA29 D7 Data
PB3 D8 Data
PB4 D9 Data
PB5 D10 Data
PB6 D11 Data
PB7 D12 Data
PB8 D13 Data
PB9 D14 Data
PB10 A0/D15 Data
PB12 A1 Address
PB13 A2 Address
PB14 A3 Address
PB15 A4 Address
PB2 RD Read
PA30 WR Write
PC6 CS Chip select
PB11 IRQ Interrupt
PB16 RESET Reset chip

The figure below depicts the connection between LAN9252 and the two EtherCAT connectors.

Figure 2. EtherCAT Connectors J13 and J14

The position of the two connectors is shown in the picture below.

Figure 3. RJ45 Connectors J13 and J14 Location