63.2.2 SPI Characteristics
- 32-data Transmit and Receive FIFOs
- Host or Client Serial Peripheral Bus Interface
- 8-bit to 16-bit programmable data length per chip select
- Programmable phase and polarity per chip select
- Programmable transfer delay between consecutive transfers and delay before SPI clock per chip select
- Programmable delay between chip selects
- Selectable Mode Fault Detection
- Host Mode Can Drive SPCK up to Peripheral Clock
- Host Mode Bit Rate Can Be Independent of the Processor/Peripheral Clock
- Client Mode Operates on SPCK, Asynchronously with Core and Bus Clock
- Four Chip Selects with External Decoder Support Allow Communication with up to 15Peripherals
- Communication with Serial External Devices Supported
- Serial memories, such as DataFlash and 3-wire EEPROMs
- Serial peripherals, such as ADCs, DACs, LCD controllers, CAN controllers and sensors
- External coprocessors
- Connection to DMA
Channels Optimizes Data Transfers
- One channel for the receiver
- One channel for the transmitter
- Functional Safety: Protection, Monitors and Reports
- Register Write protection
- Reports any write-protected access