34.6 PLL Controls
The PMC embeds 7 PLLs that are controlled by the PMC_PLL_CTRL0, PMC_PLL_CTRL1, PMC_PLL_SSR, PMC_PLL_ACR and PMC_PLL_UPDATE registers. Each PLL is accessed in read or write through its index as defined in the table below, corresponding to the register field PMC_PLL_UPDT.ID. At any time, PLL_CTRL0, PLL_CTRL1 and PLL_ACR reflect the controls for the PLL with index PMC_PLL_UPDT.ID. When the UPDATE bit is set in PMC_PLL_UPDT, the PLL of index PMC_PLL_UPDT.ID is updated with the content of registers PLL_CTRL0, PLL_CTRL1 and PLL_ACR.
Although these PLLs are identical, their implementations differ in terms of input clock signal, maximum output clock frequency or availability of a dedicated output line.
Each PLL is fed by either the MAINCK or the main crystal oscillator and has a constraint on the frequency it can generate on its clock output. Refer to the section “Electrical Characteristics”.
The table below describes all PLLs with their names and source clocks. For maximum frequency, refer to the section “Electrical Characteristics”.
| Index | PLL Name | Clock Name | PLL Clock Source | Usage Example | IO PLL Clock |
|---|---|---|---|---|---|
| 0 | CPUPLL | CPUPLLCK | MAINCK | CPU clock source | – |
| 1 | SYSPLL | SYSPLLCK | MAINCK | MCK1 clock source (matrixes, etc.) | – |
| 2 | DDRPLL | DDRPLLCK | MAINCK | Clock source (DDR Phy) | – |
| 3 | IMGPLL | IMGPLLCK | MAINCK | MCK3 clock source (Image subsystem) | – |
| 4 | BAUDPLL | BAUDPLLCK | MAINCK | GCLK source for FLEXCOM, SDMMC, etc. | – |
| 5 | AUDIOPLL | AUDIOPLLCK | MAIN XTAL OSC | AUDIOCLK output clock source | AUDIO_CLK |
| 6 | ETHPLL | ETHPLLCK | MAIN XTAL OSC | GMAC GCLK clock source | – |