60.6.3.2 Test and JTAG Pin Monitor

This monitor controls the activity on the TST, TMS/SWDIO, TCK/SWCLK and JTAGSEL pads, and on some processor pins.

If the TST pin is seen high on two consecutive ICLK clock cycles, an alarm is sent to the Protection Manager in order to start the Erase sequence.

If the JTAGSEL pin state changes either to Debug or Boundary Scan mode, an alarm is generated. Refer to EmbeddedICE^TM in the section "Debug and Test" for the polarity of the JTAGSEL pin.

If the TMS/SWDIO pin is seen high twice and seen low twice in less than 10 consecutive TCK/SWCLK clock cycles, the TCK alarm is sent to the Protection Manager in order to start the Erase sequence. This detection is used to detect some JTAG commands being issued from an external debugger.

If the DBGACK pin of the processor is seen high (signaling that the core entered Debug mode), an alarm is sent to the Protection Manager, provided SECUMOD_JTAGCR.PROC_DEBUG_MON=1.