18.3.1 Byte Lane PHY

The external memory components are designed to support byte lanes for optimal system timing. The partitioning of the data word into discrete byte lanes allows pin-to-pin skew to be managed across a much smaller group of signals than would typically be required. This eases signal track topology matching in the package and PCB environments.

The SDRAM contains data strobes associated with each 8 bits of data and there is a timing skew allowance between the main clock signal to the SDRAM and its data strobe inputs during a Write command (TDQSS):

  • 8-bit memory components provide a single DDR_DQS.
  • 16-bit memory components provide two DDR_DQSs, one for each 8 bits.

A byte lane consists of the following I/O slots:

  • 8 data bits (DDR_D[7:0])
  • Data strobe bits (DDR_DQS/DDR_DQSN)
  • 1 data mask bit (DDR_DQM)

The ITMs (Interface Timing Modules) provide a mechanism for monitoring read timing drift, which can be used to adjust timing to maintain optimum system margins. Drift analysis and compensation are performed by the controller on a per-byte lane basis. These functions operate dynamically for each data bit of every user-issued Read command. There are no overhead penalties in terms of channel bandwidth or utilization incurred by the use of these functions.

A DLL macrocell consisting of a host DLL and two client DLLs (mirror delay lines) is used at each byte lane to facilitate optimal PHY timing for drive and capture of DDR data streams, and allows the lanes to be independent. The host DLL section provides outputs for DDR data stream creation to the SDRAMs and acts as a reference for the client delay line sections. The client delay line sections translate the incoming DQS/DQS_b into the center of the read data eye to maximize read system timing margins.

The user can fine-tune the DDR_DQS and DDR_D signal relationships to maximize the read system timing margin. The DLL includes adjustability of the client delay lines for the DDR_DQS and DDR_DQSN signals, which provide byte-wide timing adjustments. The ITMs (Interface Timing Modules) include adjustability of the read DDR_DQS/DDR_DQSN strobe timing, which provides byte-wide timing adjustments. The ITMs include adjustability of the read DDR_D signal timing, which provides per-bit timing adjustability. To enable lane-independent timing adjustments, DLL adjustment bits are provided by the controller per byte lane, and ITM adjustment bits are provided per bit.

The DDR-specific SSTL I/Os include programmable ODT and output impedance selection. The ODT and output impedances can be dynamically calibrated to compensate for variations in voltage and temperature.

The ODT feature can be disabled by the controller. When ODT is enabled by the controller, the SSTL I/O automatically enables its internal ODT circuitry when in Input mode and disables this circuitry when in Output mode. The initial programming and subsequent calibration of the ODT and output impedance can be triggered to calibrate the ODT and output impedance values at the I/Os based on the desired impedance value when compared to a precision external resistor.