25.5.1 Real-Time Timer Mode Register

This register can only be written if the WPEN bit is cleared in the System Controller Write Protection Mode register (SYSC_WPMR).

Name:	RTT_MR
Offset:	0x00
Reset:	0x00008000
Property:	Read/Write


Bit	31	30	29	28	27	26	25	24
								RTC1HZ
Access								R/W
Reset								0


Bit	23	22	21	20	19	18	17	16
			INC2AEN	RTTDIS		RTTRST	RTTINCIEN	ALMIEN
Access			R/W	R/W		R/W	R/W	R/W
Reset			0	0		0	0	0


Bit	15	14	13	12	11	10	9	8
	RTPRES[15:8]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	1	0	0	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
	RTPRES[7:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bit 24 – RTC1HZ Real-Time Clock 1Hz Clock Selection

Value	Description
0	The RTT 32-bit counter is driven by the 16-bit prescaler roll-over events.
1	The RTT 32-bit counter is driven by the 1Hz RTC clock.

Bit 21 – INC2AEN RTTINC2 Alarm and Interrupt Enable

Value	Description
0	The RTTINC2 flag is not a source of the RTT alarm signal nor a source of interrupt.
1	The RTTINC2 flag is a source of the RTT alarm signal and a source of interrupt.

Bit 20 – RTTDIS Real-Time Timer Disable

Value	Description
0	The RTT is enabled.
1	The RTT is disabled (no dynamic power consumption).

Bit 18 – RTTRST Real-Time Timer Restart

Value	Description
0	No effect.
1	Reloads and restarts the clock divider with the new programmed value. This also resets the 32-bit counter.

Bit 17 – RTTINCIEN Real-Time Timer Increment Interrupt Enable

Value	Description
0	The RTT_SR.RTTINC bit has no effect on interrupt.
1	The RTT_SR.RTTINC bit asserts interrupt.

Bit 16 – ALMIEN Alarm Interrupt Enable

Value	Description
0	The RTT_SR.ALMS bit has no effect on interrupt.
1	The RTT_SR.ALMS bit asserts interrupt.

Bits 15:0 – RTPRES[15:0] Real-Time Timer Prescaler Value

Defines the number of RTT slow clock periods required to increment the Real-Time Timer. The RTTINCIEN bit must be cleared prior to writing a new RTPRES value.

RTPRES is defined as follows:

RTPRES = 0: The prescaler period is equal to 2¹⁶ * slow clock periods.
RTPRES = 1 or 2: forbidden.
RTPRES ≠ 0, 1 or 2: The prescaler period is equal to RTPRES * slow clock periods.