20.3.1 Clocks

All system controller peripherals, except the 6x PIT64B instances, are part of the CPU System and Security (CSS) matrix that runs on MCK0.

Note: The MCK0 frequency is directly related to the CPU clock, so any change on the CPU clock impacts MCK0.

The system controller peripherals are always on, except:

  • Parallel Input/Output Controllers (PIOs) that have one clock control (PIOA) for all PIO controllers, clocked with MCK0
  • Special Function Registers (SFR)

PIT64B0 to PIT64B5 are located on the APB Client (APS) matrix, clocked with MCK1.

In addition, PIT64B0 to PIT64B5 feature a GCLK input for flexibility. CA7 Base Time (GCLK ID29), defined as MAINCK, is automatically started at reset.