33.5.1 Slow Clock Controller Configuration Register
| Name: | SCKC_CR |
| Offset: | 0x0 |
| Reset: | 0x00000001 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| TD_OSCSEL | |||||||||
| Access | R/W | ||||||||
| Reset | 0 |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| Access | |||||||||
| Reset |
Bit 24 – TD_OSCSEL Timing Domain Slow Clock Selector
| Value | Description |
|---|---|
| 0 (RC) | Slow clock of the timing domain is driven by the embedded Always-on 64 kHz (typical) RC oscillator. |
| 1 (XTAL) | Slow clock of the timing domain is driven by the 32.768 kHz crystal oscillator. |