17.1 Description

The SDRAM memory interface is made of:

the Universal DDR Memory Controller (UDDRC) and
the PHYsical layer interface (DDR3PHY).

The UDDRC receives transactions from the internal buses. These transactions are queued internally and scheduled for access in order to the DDR-SDRAM while satisfying the DDR-SDRAM protocol timing requirements, transaction priorities, and dependencies between transactions.

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