23.4.8 Watchdog Halt
While the processor is in Debug state or in Sleep mode (including ULP mode 1 and 2), the counter may be stopped depending on the value programmed for the bits WDIDLEHLT and WDDBGHLT in PSWDT_MR or NSWDT_MR.
While the processor is in Debug state or in Sleep mode (including ULP mode 1 and 2), the counter may be stopped depending on the value programmed for the bits WDIDLEHLT and WDDBGHLT in PSWDT_MR or NSWDT_MR.
The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.