55.2 Embedded Characteristics

  • Supports Secure Hash Algorithm (SHA1, SHA224, SHA256, SHA384, SHA512, SHA512/224, SHA512/256)
  • Supports Hash-based Message Authentication Code (HMAC) Algorithm (HMAC-SHA1, HMAC-SHA224, HMAC-SHA256, HMAC-SHA384, HMAC-SHA512, HMAC-SHA512/224, HMAC-SHA512/256)
  • Compliant with FIPS Publication 180-4
  • Supports Automatic Padding of Messages
  • Supports Up to 2 Sets of Initial Hash Values Registers (HMAC Acceleration or other)
  • Supports Automatic Check of the Hash (HMAC Acceleration or other)
  • Tightly Coupled to AES for Protocol Layers Improved Performances
  • Configurable Processing Period:
    • 85 clock cycles to obtain a fast SHA1 runtime, 88 clock cycles for SHA384, SHA512 or 209 Clock Cycles for Maximizing Bandwidth of Other Applications
    • 72 clock cycles to obtain a fast SHA224, SHA256 runtime or 194 clock cycles for maximizing bandwidth of other applications
  • Connection to DMA Channel Capabilities Optimizes Data Transfers
  • Double Input Buffer Optimizes Runtime
  • Register Write Protection